The present invention relates to a semiconductor memory device of a redundancy configuration enabling substitution for defective bits or memory cells, and particularly to an improvement for reducing an access time in a static column mode.
FIG. 1 shows a conventional semiconductor memory with a redundancy configuration for correcting defect, as disclosed in Japanese Patent Application Publication No. 8520/1986. As illustrated, it comprises a row of sense amplifiers 1, an array 2 of spare memory cells 2', an array 3 of normal memory cells which may include a defective memory cell 3'. The memory device further comprises a word line drive circuit 4, a row decoder 6, a comparator 6 having signal path interrupter element 6' which may be in the form of a fuse blown or unblown by laser beam or the like depending on the corresponding bit of the address of a defective memory cell. More specifically, a set of signal path interrupter elements 6' are broken (blown) or unbroken (unblown) so that the code as represented by the set correspond to the address of the detective row for which the spare row is substituted. The signal path interrupter element 6' will be called a pROM element. The memory device further comprises a row decoder inhibiting circuit 7, a control signal generator circuit 8, a word line clock generator 9, a dummy decoder 10 for adjusting (by introducing delay) the timing of activation of word line clock generator 9, a multiplexer 11, a column decoder 12 and a data input/output butter circuit 13. The memory device further comprises data input/output lines 14, bit lines 15, spare word lines 16 and word lines 17. .phi..sub.p represents a precharge clock and .phi.red is a signal which is at "L" level (low voltawe level) only when redundancy correction of the defective bit is made.
The memory reading operation with a defective bit being corrected will be described. It is assumed that a defective memory cell 3' is replaced by a spare memory cell 2' on the same bit line 15 to which the defective memory cell 3' is also connected.
When an address buffer output signal (hereinafter abbreviated as "address signal") is input to the row decoder 5 and the comparator 6. The comparator 6 compares the input address with the address programmed by the PROM elements 6', and when finding coincidence, produces an output for activating the control signal generator circuit 8.
The control signal generator circuit 8 activates the row decoder inhibiting circuit 7 and the dummy decoder 10. The output of the dummy decoder 10 is established at the timing when the row decoder 5 stops its function upon operation of the row decoder inhibiting circuit 7. The output of the dummy decoder 10 activates the word line clock generator 9, whereupon the word line drive clock thereby generated activates the word line drive circuit 4. By then, The row decoder 5 has been inactivated by the row decoder inhibiting circuit 7 so that the word line drive circuit 4 connected to the row decoder 5 maintains low the word line 17 that is connected to the word line drive circuit 4.
The spare word line 16 is made high (high voltage level) by the word line drive circuit 4, and minute signal voltages corresponding to the respective cell data of one row of the spare memory cell array 2 connected to the spare word line 16 appear on all the bit lines. Thereafter the row of sense amplifiers 1 are activated to amplify the minute signals, which are then transmitted to the multiplexer 11. The multiplexer 11 selects the cell data of the spare memory cell 2' connected to the bit line 15 in accordance with the select signal of the column decoder 12, and the selected cell data is supplied through the data input/output line 14 to the data input/output buffer 13. The cell data is thus read out.
Although only one comparator 6 is illustrated, there are actually the same number of comparators 6 as the number of spare memory rows, and each comparator 6 produces a signal when the address buffer output signal is identical to the address programmed by the PROM elements 6' in the particular comparator 6.
Although only one each of the dummy decoder 10 and the word line clock generator 9 is illustrated, there are actually four dummy decoders 10 selected by the address buffer output signal, and four word line clock generators 9 corresponding to the respective dummy decoders 10.
In the above-described semiconductor memory device, a precharge period is required in which the comparator is initialized before comparing the input address with the programmed address. During this precharge period, the address buffer output signal input to the comparator 6 must be kept low. and after the precharge period, the address buffer output is activated whereupon the comparator 6 operates to carry out the comparison. In a semiconductor memory device with a redundancy configuration for row addresses, the precharge can be implemented in synchronism with a strobe signal such as RAS before the row address is determined. However, in a static column mode, the address of the memory cell which are read out is chanwed responsive to the change in the address signal, once a row has been selected by a RAS signal. In such a static column mode, the address buffer output must be made low after change of the external input address, and the precharge must be made, before the address buffer output is activated to cause the comparator operation. Thus with the conventional redundancy configuration with the comparator requiring a precharge period before activation of the address buffer output, it is difficult to reduce the time (access time) from the change in the column address in the static column mode to the read-out of the data.